1. Field of Use
The present invention relates to apparatus for performing floating point operations on numbers represented in binary coded form and more particularly to apparatus for performing floating point operations using microprocessor chips including multiple storage.
2. Prior Art
The prior art discloses numerous ways for performing multiplication operations which involve initially generating a percentage of the total number of submultiples of an operand, storing these and then generating the remaining multiples from selected combinations of the prestored multiples. U.S. Pat. No. 3,293,419 is illustrative of this type of arrangement.
U.S. Pat. No. 3,641,331 provided apparatus which generated and stored a predetermined number of multiples and generated the remaining multiples by performing a single operation upon a selected prestored multiple. While the apparatus of the patent could be more easily constucted and reduced the time required for performing multiplication operations, it did not lend itself readily to construction in large scale integration (LSI) or medium scale integration (MSI) form.
However, certain semiconductor manufacturers have developed standard microprocessor chips which have reduced significantly the costs of constructing high speed arithmetic units.
For example, Advanced Micro Devices Inc. developed a 4 bit bipolar microprocessor slice on a chip designated as an AM2901. These chips when connected in parallel make it possible to carry out multiplication a bit at a time. Such an arrangement is described in a publication titled "4 Bit Expandable Bipolar Microcontroller 5701/6701" by Monolithic Memories Inc. dated May 1974. Such arrangements by being limited by the number of multiplier bits which can be processed in parallel are required to be operated at speeds slower than the previously described arrangements. In order to increase the number of multiplier bits which could be processed at a time, it would be necessary to modify such chips and increase the number of pins with attendant increases in chip costs.
Accordingly, it is a primary object of the present invention to provide an improved apparatus including means for generating and storing selective multiples of an operand and generate all required multiples of the operand as required by the operation within a minimum period of time.
It is a further object of the present invention to provide apparatus which can be constructed with standard microprocessor chips and which generates all multiples of a multiplicand during the performance of a multiplication operation.
It is a more specific object of the present invention to provide a low cost apparatus for performing floating point multiplication operations at high speed.